Design and Simulation of 64 Bit Divider Using Vedic Mathematics

The idea for designing the Divider unit is adopted from ancient Indian mathematics "Vedas" .Vedic Mathematics is the old method of computing. With the advent of new technology in the fields of VLSI and communication, there is also an always increasing demand for high speed processing and low area design. Divider is an important fundamental function in arithmetic operations. It is also known fact that the Divider unit forms an integral part of processor design. Due to this regard, high speed Divider architectures become the need of the day. In this, we introduce a performance of the device with various methods of Vedic Mathematics .The methods used in this are faster than the Normal methods of Division. The functionality of these circuits was checked and performance parameters were calculated. The design and experiments were carried out on a Xilinx and implementation of FPGA and the timing and area of the design, on the same parameters have been calculated. Keywords— Nikhilam Navatascaramam Dasatah (NND), Paravartya Yojayet, Flagpole (Dhvajanka), Vedic Mathematics.